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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">cy_stc_tdm_config_tx_t Struct Reference<div class="ingroups"><a class="el" href="group__group__tdm.html">TDM/I2S      (Time Division Multiplexing/Inter-IC Sound)</a> &raquo; <a class="el" href="group__group__tdm__data__structures.html">Data Structures</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>TDM Initialization configuration. </p>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a3bc0d8a5a0059e0012490022c3f06a3d"><td class="memItemLeft" align="right" valign="top"><a id="a3bc0d8a5a0059e0012490022c3f06a3d"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#a3bc0d8a5a0059e0012490022c3f06a3d">enable</a></td></tr>
<tr class="memdesc:a3bc0d8a5a0059e0012490022c3f06a3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables/Disables TDM TX. <br /></td></tr>
<tr class="separator:a3bc0d8a5a0059e0012490022c3f06a3d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1826efa7dbe3da948371ac205cfb272b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__tdm__enums.html#gacf788712265d4ce0fdbf0b9aed4bb38f">cy_en_tdm_device_cfg_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#a1826efa7dbe3da948371ac205cfb272b">masterMode</a></td></tr>
<tr class="memdesc:a1826efa7dbe3da948371ac205cfb272b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master mode/Slave mode configuration.  <a href="#a1826efa7dbe3da948371ac205cfb272b">More...</a><br /></td></tr>
<tr class="separator:a1826efa7dbe3da948371ac205cfb272b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0a4251c3863764fcad2e6d42efc5e483"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__tdm__enums.html#ga3e7c9522bd7a7e179487ac26fcec0129">cy_en_tdm_ws_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#a0a4251c3863764fcad2e6d42efc5e483">wordSize</a></td></tr>
<tr class="memdesc:a0a4251c3863764fcad2e6d42efc5e483"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX word length.  <a href="#a0a4251c3863764fcad2e6d42efc5e483">More...</a><br /></td></tr>
<tr class="separator:a0a4251c3863764fcad2e6d42efc5e483"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac0faea2467c11b49ebd1d64f9c97ca71"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__tdm__enums.html#ga17c76544100c74ac3f72bd1a23131acf">cy_en_tdm_format_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#ac0faea2467c11b49ebd1d64f9c97ca71">format</a></td></tr>
<tr class="memdesc:ac0faea2467c11b49ebd1d64f9c97ca71"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX data format, <a class="el" href="group__group__tdm__enums.html#ga17c76544100c74ac3f72bd1a23131acf">cy_en_tdm_format_t</a>.  <a href="#ac0faea2467c11b49ebd1d64f9c97ca71">More...</a><br /></td></tr>
<tr class="separator:ac0faea2467c11b49ebd1d64f9c97ca71"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae13301494d245facd3e6f5e02e1652ca"><td class="memItemLeft" align="right" valign="top">uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#ae13301494d245facd3e6f5e02e1652ca">clkDiv</a></td></tr>
<tr class="memdesc:ae13301494d245facd3e6f5e02e1652ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Should be set to an even value ({2, 4, 6, ..., 256}), to ensure a 50/50% duty cycle clock.  <a href="#ae13301494d245facd3e6f5e02e1652ca">More...</a><br /></td></tr>
<tr class="separator:ae13301494d245facd3e6f5e02e1652ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a14099f700bc3514d8debdaae4bd127"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__tdm__enums.html#ga6e68e27138e141adeaca8402fd032e37">cy_en_tdm_clock_sel_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#a1a14099f700bc3514d8debdaae4bd127">clkSel</a></td></tr>
<tr class="memdesc:a1a14099f700bc3514d8debdaae4bd127"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface clock "clk_if" selection, <a class="el" href="group__group__tdm__enums.html#ga6e68e27138e141adeaca8402fd032e37">cy_en_tdm_clock_sel_t</a>.  <a href="#a1a14099f700bc3514d8debdaae4bd127">More...</a><br /></td></tr>
<tr class="separator:a1a14099f700bc3514d8debdaae4bd127"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a869ecdc8ea834d943e6697ac805e46a3"><td class="memItemLeft" align="right" valign="top"><a id="a869ecdc8ea834d943e6697ac805e46a3"></a>
<a class="el" href="group__group__tdm__enums.html#ga740465810e855730300bda1ca68a3f29">cy_en_tdm_sckpolarity_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#a869ecdc8ea834d943e6697ac805e46a3">sckPolarity</a></td></tr>
<tr class="memdesc:a869ecdc8ea834d943e6697ac805e46a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX clock polarity, 0: as is and 1: inverted <a class="el" href="group__group__tdm__enums.html#ga740465810e855730300bda1ca68a3f29">cy_en_tdm_sckpolarity_t</a>. <br /></td></tr>
<tr class="separator:a869ecdc8ea834d943e6697ac805e46a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2613f222b739ffa08956452b746dcb73"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__tdm__enums.html#gae049ad85366a084a1bbf3ef69109c0c5">cy_en_tdm_fsyncpolarity_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#a2613f222b739ffa08956452b746dcb73">fsyncPolarity</a></td></tr>
<tr class="memdesc:a2613f222b739ffa08956452b746dcb73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Synchronization polarity:0:as is 1:inverted.  <a href="#a2613f222b739ffa08956452b746dcb73">More...</a><br /></td></tr>
<tr class="separator:a2613f222b739ffa08956452b746dcb73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7e32da17f5022c64615fafa4d4a3a8fa"><td class="memItemLeft" align="right" valign="top"><a id="a7e32da17f5022c64615fafa4d4a3a8fa"></a>
<a class="el" href="group__group__tdm__enums.html#ga0beaff668ba6388ecccaf62524a37449">cy_en_tdm_fsyncformat_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#a7e32da17f5022c64615fafa4d4a3a8fa">fsyncFormat</a></td></tr>
<tr class="memdesc:a7e32da17f5022c64615fafa4d4a3a8fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel synchronization pulse format <a class="el" href="group__group__tdm__enums.html#ga0beaff668ba6388ecccaf62524a37449">cy_en_tdm_fsyncformat_t</a>. <br /></td></tr>
<tr class="separator:a7e32da17f5022c64615fafa4d4a3a8fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a188b3bdb661511f30b99b86118813642"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#a188b3bdb661511f30b99b86118813642">channelNum</a></td></tr>
<tr class="memdesc:a188b3bdb661511f30b99b86118813642"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of channels in the frame: 1 to 32 channels supported.  <a href="#a188b3bdb661511f30b99b86118813642">More...</a><br /></td></tr>
<tr class="separator:a188b3bdb661511f30b99b86118813642"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a04fec5dc3d10f0bb7d8f1a52a4b6e457"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#a04fec5dc3d10f0bb7d8f1a52a4b6e457">channelSize</a></td></tr>
<tr class="memdesc:a04fec5dc3d10f0bb7d8f1a52a4b6e457"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel Size.  <a href="#a04fec5dc3d10f0bb7d8f1a52a4b6e457">More...</a><br /></td></tr>
<tr class="separator:a04fec5dc3d10f0bb7d8f1a52a4b6e457"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a183ea391fe430018453adff41c8f1af1"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#a183ea391fe430018453adff41c8f1af1">fifoTriggerLevel</a></td></tr>
<tr class="memdesc:a183ea391fe430018453adff41c8f1af1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Trigger level.  <a href="#a183ea391fe430018453adff41c8f1af1">More...</a><br /></td></tr>
<tr class="separator:a183ea391fe430018453adff41c8f1af1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae6979593de0f9046da4f995719ab96c5"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#ae6979593de0f9046da4f995719ab96c5">chEn</a></td></tr>
<tr class="memdesc:ae6979593de0f9046da4f995719ab96c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channels enabled: channel i is controlled by bit chEn[i].  <a href="#ae6979593de0f9046da4f995719ab96c5">More...</a><br /></td></tr>
<tr class="separator:ae6979593de0f9046da4f995719ab96c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aef31976c1428b40f0c89e8a73c605c65"><td class="memItemLeft" align="right" valign="top"><a id="aef31976c1428b40f0c89e8a73c605c65"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#aef31976c1428b40f0c89e8a73c605c65">signalInput</a></td></tr>
<tr class="memdesc:aef31976c1428b40f0c89e8a73c605c65"><td class="mdescLeft">&#160;</td><td class="mdescRight">Controls routing to the TX slave signaling inputs (FSYNC/SCK): '0': TX slave signaling independent from RX signaling : '1': TX slave signaling inputs driven by RX Slave: '2': TX slave signaling inputs driven by RX Master: <br /></td></tr>
<tr class="separator:aef31976c1428b40f0c89e8a73c605c65"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a04a7cbb9405483d5965759d640b380c8"><td class="memItemLeft" align="right" valign="top"><a id="a04a7cbb9405483d5965759d640b380c8"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__tx__t.html#a04a7cbb9405483d5965759d640b380c8">i2sMode</a></td></tr>
<tr class="memdesc:a04a7cbb9405483d5965759d640b380c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">IF set to 1 the IP is configured for I2S mode else for TDM mode. <br /></td></tr>
<tr class="separator:a04a7cbb9405483d5965759d640b380c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Field Documentation</h2>
<a id="a1826efa7dbe3da948371ac205cfb272b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1826efa7dbe3da948371ac205cfb272b">&#9670;&nbsp;</a></span>masterMode</h2>

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          <td class="memname"><a class="el" href="group__group__tdm__enums.html#gacf788712265d4ce0fdbf0b9aed4bb38f">cy_en_tdm_device_cfg_t</a> cy_stc_tdm_config_tx_t::masterMode</td>
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<p>Master mode/Slave mode configuration. </p>
<p><a class="el" href="group__group__tdm__enums.html#gacf788712265d4ce0fdbf0b9aed4bb38f">cy_en_tdm_device_cfg_t</a> </p>

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<a id="a0a4251c3863764fcad2e6d42efc5e483"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0a4251c3863764fcad2e6d42efc5e483">&#9670;&nbsp;</a></span>wordSize</h2>

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          <td class="memname"><a class="el" href="group__group__tdm__enums.html#ga3e7c9522bd7a7e179487ac26fcec0129">cy_en_tdm_ws_t</a> cy_stc_tdm_config_tx_t::wordSize</td>
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<p>TX word length. </p>
<p>Channel size must be greater or equal to the word size. </p>

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<a id="ac0faea2467c11b49ebd1d64f9c97ca71"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac0faea2467c11b49ebd1d64f9c97ca71">&#9670;&nbsp;</a></span>format</h2>

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          <td class="memname"><a class="el" href="group__group__tdm__enums.html#ga17c76544100c74ac3f72bd1a23131acf">cy_en_tdm_format_t</a> cy_stc_tdm_config_tx_t::format</td>
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<p>TX data format, <a class="el" href="group__group__tdm__enums.html#ga17c76544100c74ac3f72bd1a23131acf">cy_en_tdm_format_t</a>. </p>

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<a id="ae13301494d245facd3e6f5e02e1652ca"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae13301494d245facd3e6f5e02e1652ca">&#9670;&nbsp;</a></span>clkDiv</h2>

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          <td class="memname">uint16_t cy_stc_tdm_config_tx_t::clkDiv</td>
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<p>Should be set to an even value ({2, 4, 6, ..., 256}), to ensure a 50/50% duty cycle clock. </p>
<p>Only for Master Mode </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a1a14099f700bc3514d8debdaae4bd127">&#9670;&nbsp;</a></span>clkSel</h2>

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          <td class="memname"><a class="el" href="group__group__tdm__enums.html#ga6e68e27138e141adeaca8402fd032e37">cy_en_tdm_clock_sel_t</a> cy_stc_tdm_config_tx_t::clkSel</td>
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<p>Interface clock "clk_if" selection, <a class="el" href="group__group__tdm__enums.html#ga6e68e27138e141adeaca8402fd032e37">cy_en_tdm_clock_sel_t</a>. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a2613f222b739ffa08956452b746dcb73">&#9670;&nbsp;</a></span>fsyncPolarity</h2>

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<p>Synchronization polarity:0:as is 1:inverted. </p>
<p><a class="el" href="group__group__tdm__enums.html#gae049ad85366a084a1bbf3ef69109c0c5">cy_en_tdm_fsyncpolarity_t</a> </p>

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<a id="a188b3bdb661511f30b99b86118813642"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a188b3bdb661511f30b99b86118813642">&#9670;&nbsp;</a></span>channelNum</h2>

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          <td class="memname">uint8_t cy_stc_tdm_config_tx_t::channelNum</td>
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<p>Number of channels in the frame: 1 to 32 channels supported. </p>
<p>In I2S mode number of channels should be 2. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a04fec5dc3d10f0bb7d8f1a52a4b6e457">&#9670;&nbsp;</a></span>channelSize</h2>

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<p>Channel Size. </p>
<p>Channel size must be greater or equal to the word size. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a183ea391fe430018453adff41c8f1af1">&#9670;&nbsp;</a></span>fifoTriggerLevel</h2>

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          <td class="memname">uint8_t cy_stc_tdm_config_tx_t::fifoTriggerLevel</td>
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<p>Trigger level. </p>
<p>When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ae6979593de0f9046da4f995719ab96c5">&#9670;&nbsp;</a></span>chEn</h2>

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<p>Channels enabled: channel i is controlled by bit chEn[i]. </p>
<p>For example : In I2S mode for 2 channels the chEn will be 0x3 </p>

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